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PRELIMINARY INFORMATION
ICS548-05A MP3 Audio Clock
Description
The ICS548-05 is a low cost, low jitter, high performance clock synthesizer designed to produce audio sampling rates for MP3 systems. Using ICS' patented analog/digital Phase-Locked Loop (PLL) techniques, the device uses an inexpensive 3.6864 MHz crystal or clock input to exactly produce all of the popular audio sampling frequencies. Power down modes allow the chip to be turned off completely, or the PLL and audio clock output to be turned off separately. ICS manufactures the largest variety of multimedia clock synthesizers for all applications. Consult ICS to eliminate VCXOs, crystals and oscillators from your board.
Features
* Packaged in 16 pin TSSOP * Ideal for Cirrus Logic's MP3 chips * Replaces multiple oscillators * 3.3V (will work down to 2.7V) or 5V operation * Uses an inexpensive 3.6864 MHz crystal or clock input * Supports 32 kHz, 44.1 kHz, 48 kHz, and 96 kHz audio sampling rates * Provides 128fs and 256fs clocks * Zero ppm synthesis error * Includes Power Down features * Advanced, low power, sub-micron CMOS process
Block Diagram
S3:S0 REFEN PDCLK
X1
4
PLL/Clock Synthesis Circuitry
Output Buffer
CLK
3.6864 MHz crystal or clock
Crystal Oscillator
X2
Output Buffer
REFOUT
Optional crystal capacitors
MDS 548-05 AC
1
Revision 032900
Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel * www.icst.com
PRELIMINARY INFORMATION
ICS548-05A MP3 Audio Clock
Pin Assignment
Output Clock Select Table
S3 Pin 7 0 0 1 1 1 1 1 1 1 1 S2 S1 S0 Input (MHz) CLK (MHz) Pin 8 Pin 12 Pin 13 Pins 1, (16) Pin 9 0 1 0 3.6864 2.8224 0 1 1 3.6864 3.072 0 0 0 3.6864 4.096 0 0 1 3.6864 5.6448 0 1 0 3.6864 6.144 0 1 1 Turns off PLL and stops CLK low 1 0 0 3.6864 8.192 1 0 1 3.6864 11.2896 1 1 0 3.6864 12.288 1 1 1 3.6864 2.048
ICS548-05A
X1/ICLK VDD VDD REFEN GND GND S3 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 DC REFOUT S0 S1 PDCLK DC CLK
16 pin TSSOP
Power Down Clock Select Table
REFEN Pin 4 0 0 1 1 PDCLK Pin 11 0 1 0 1 Power Down Selection Mode The entire chip is off. PLL and CLK output run, REFOUT low. REFOUT running, PLL off, CLK low. All running.
Key:
0 = connect directly to GND 1 = connect directly to VDD
Pin Descriptions
Number 1 2, 3 4 5, 6 7 8 9 10, 15 11 12 13 14 16 Name X1/ICLK VDD REFEN GND S3 S2 CLK DC PDCLK S1 S0 REFOUT X2 Type XI P I P I I O I I I O XO Description Crystal connection. Connect to a 3.6864 MHz crystal, or input clock. Connect to +3.3V or +5V. All VDDs must be same. Reference Clock Enable. See above table. Connect to ground. Frequency select pin 3. Determines clock outputs per table above. Frequency select pin 2. Determines clock outputs per table above. Audio clock output set by status of S0-S3. See table above. Don't Connect. Do not connect anything to these pins. Power Down Clock. See above table. Frequency select pin 1. Determines clock outputs per table above. Frequency select pin 0. Determines clock outputs per table above. Buffered 3.6864 MHz oscillator output clock. Controlled by REFEN. Crystal connection. Connect to a 3.6864 MHz crystal, or leave unconnected for clock.
Key: I = Input; O = output; P = power supply connection; XI, XO = crystal connections The input pins S3:S0 lack pull-ups, so they cannot be left floating. Tie directly to VDD or GND. For a clock input, connect the input to X1, and leave X2 unconnected (floating).
MDS 548-05 AC
2
Revision 032900
Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel * www.icst.com
PRELIMINARY INFORMATION
ICS548-05A MP3 Audio Clock
Typical Maximum 7 VDD+0.5 70 260 150 5.5 VDD/2 VDD/2 (VDD/2)-1 0.8 Units V V C C C V V V V V V V V mA A mA pF ppm
Electrical Specifications
Parameter Supply voltage, VDD Inputs and Clock Outputs Ambient Operating Temperature Soldering Temperature Storage temperature Core Operating Voltage, VDD Input High Voltage, VIH, X1/ICLK pin Input Low Voltage, VIL, X1/ICLK pin Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH, CMOS level Operating Supply Current, IDD Power Down Supply Current, IDDPD Short Circuit Current Input Capacitance Frequency synthesis error Conditions Referenced to GND Referenced to GND Max of 10 seconds -65 2.7 (VDD/2)+1 2 IOH=-12mA IOL=12mA IOH=-4mA No Load No Load CLK output S0, S1, S2, S3, PDCLK All selections 2.4 0.4 VDD-0.4 4 5 50 7 0 Minimum
ABSOLUTE MAXIMUM RATINGS (note 1)
-0.5 0
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Clock input only Clock input only
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Crystal or Clock Frequency 3.6864 MHz Output Clock Rise Time 0.8 to 2.0V 2 ns Output Clock Fall Time 2.0 to 0.8V 2 ns Output Clock Duty Cycle At VDD/2 40 50 60 % Start-up Time VDD=3V to CLK stable 10 ms Maximum Absolute Jitter, short term 250 ps One sigma jitter 70 ps Note: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components/ Application Information
The ICS548-05 requires a minimum number of external components for proper operation. A decoupling capacitor of 0.01F should be connected between VDD and GND on pins 3 and 5, as close to the ICS548-05 as possible. Other VDDs can be connected to pin 3. A series termination resistor of 33 may be used for each clock output. If REFOUT is not used, then REFEN should be connected to ground. The input crystal must be connected as close to the chip as possible. The input crystal should be fundamental mode, parallel resonant. For exact accuracy of the output frequencies, the crystal can be tuned with two identical capacitors to ground, as shown on the block diagram. The value of these two crystal caps should be equal to (CL -6)*2, where CL is the crystal load (or correlation) capacitance.
MDS 548-05 AC
3
Revision 032900
Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel * www.icst.com
PRELIMINARY INFORMATION
ICS548-05A MP3 Audio Clock
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC publication no. 95.) 16 pin TSSOP
Inches Symbol Min Max A -0.047 A1 0.002 0.006 b 0.007 0.012 c 0.0035 0.008 D 0.193 0.201 e .025 BSC E .252 BSC E1 0.169 0.177 L 0.018 0.030 Millimeters Min Max -1.19 0.05 0.15 0.18 0.30 0.09 0.20 4.90 5.11 0.65 BSC 6.40 BSC 4.29 4.50 0.46 0.76
E1
E
INDEX AREA
1
2
D A1 e b c
A L
Ordering Information
Part/Order Number ICS548G-05 ICS548G-05T Marking 548G-05 548G-05 Shipping packaging tubes tape and reel Package 16 pin TSSOP 16 pin TSSOP Temperature 0-70 C 0-70 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 548-05 AC
4
Revision 032900
Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel * www.icst.com

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